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FSTUD16450 Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting
January 2001 Revised October 2006
FSTUD16450 Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting
General Description
The Fairchild Universal Bus Switch FSTUD16450 provides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The FSTUD16450 is designed to allow "customer" configuration control of the enable connections. The device is organized as either a 4-bit, 5-bit, 10-bit or 20-bit bus switch. 8-bit and 16-bit configurations are also achievable (see Functional Description). The device's bit configuration is chosen through select pin logic. (see Truth Table). When OEx is LOW, Port Ax is connected to Port Bx. When OEx is HIGH, the switch is OPEN. The A and B Ports are "undershoot hardened" with UHC(R) protection to support an extended range to 2.0V below ground. Fairchild's integrated "Undershoot Hardened Circuit" (UHC) senses undershoot at the I/Os, and responds by preventing voltage differentials from developing and turning on the switch. Another key device feature is the addition of a level shifting select pin, "S2". When S2 is LOW, the device behaves as a standard N-MOS switch. When S2 is HIGH, a diode to VCC is integrated into the circuit allowing for level shifting between 5V inputs and 3.3V outputs.
Features
s Undershoot hardened to -2V (A and B Ports) s Voltage level shifting s 4 switch connection between two ports s Minimal propagation delay through the switch s Low lCC s Zero bounce in flow-through mode s Control inputs compatible with TTL level s See Applications Note AN-5008 for details s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)
Applications Note
Select pins S0, S1, S2 are intended to be used as static user configurable control pins. The AC performance of these pins has not been characterized or tested. Switching of these select pins during system operation may temporarily disrupt output logic states and/or enable pin controls.
Ordering Code:
Order Number FSTUD16450GX (Note 1) FSTUD16450MTD Package Number BGA54A (Preliminary) MTD56 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Note 1: BGA package available in Tape and Reel only.
UHC(R) is a registered trademark of Fairchild Semiconductor Corporation.
(c) 2001 Fairchild Semiconductor Corporation
DS500391
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FSTUD16450
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Name OE1, OE2 1A, 2A 1B, 2B S0 , S1 S2 NC Description Bus Switch Enables Bus A Bus B Bit Configuration Enables Level Shifting Diode Enable No Connect
FBGA Pin Assignments
1 A B C D E F G H J 1A3 1A5 1A7 1A9 2A1 2A3 2A5 2A7 2A9 2 1A2 1A4 1A6 1A8 1A10 2A2 2A4 2A6 2A8 3 OE1 1A1 GND GND S0 S1 VCC 2A10 OE4 4 OE2 1B1 OE5 VCC VCC S2 GND 2B10 OE3 5 1B2 1B4 1B6 1B8 1B10 2B2 2B4 2B6 2B8 6 1B3 1B5 1B7 1B9 2B1 2B3 2B5 2B7 2B9
Pin Assignment for FBGA
(Top Thru View)
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Logic Diagrams
20-Bit Configuration (Configuration 1)
10-Bit Configuration (Configuration 2)
5-Bit Configuration (Configuration 3)
4-Bit Configuration (Configuration 4)
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FSTUD16450
Functional Description
The device can also be configured as an 8 and 16-bit device by grounding the unused pins in Configurations 2 and 1 respectively. The 8-bit configuration may also be achieved by tying two of the 4-bit enables from configuration together and tying the remaining enable pin (OE) HIGH.
Truth Tables
(X = VCC or GND) Select Pin S2 L H S0 = S1 = L Inputs OE3 X X OE4 X X S0 = L, S1 = H Inputs OE3 X X X X OE4 L H L H OE5 X X X X OE5 X X Mode Std. NMOS Switch Level Shifting Diode Enabled
(see Functional Description)
Configuration 1
20-Bit Configuration Inputs/Outputs 1A1-10 = 1B1-10, 2A1-10 = 2B1-10 Z
OE1 L H
OE2 X X
Configuration 2
10-Bit Configuration Inputs/Outputs 1A1-10 = 1B1-10 1AX = 1BX 1AX = 1BX Z Z 2A1-10 = 2B1-10 2AX = 2BX Z 2AX = 2BX Z
OE1 L L H H
OE2 X X X X
Configuration 3 Inputs OE1 L L L L L L L L H H H H H H H H OE2 L L L L H H H H L L L L H H H H OE3 L L H H L L H H L L H H L L H H
S0 = H, S1 = L OE4 L H L H L H L H L H L H L H L H OE5 X X X X X X X X X X X X X X X X 1A1-5, 1B1-5 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx Z Z Z Z Z Z Z Z
5-Bit Configuration Inputs/Outputs 1A6-10, 1B6-10 1Ay = 1By 1Ay = 1By 1Ay = 1By 1Ay = 1By Z Z Z Z 1Ay = 1By 1Ay = 1By 1Ay = 1By 1Ay = 1By Z Z Z Z 2A1-5, 2B1-5 2Ax = 2Bx 2Ax = 2Bx Z Z 2Ax = 2Bx 2Ax = 2Bx Z Z 2Ax = 2Bx 2Ax = 2Bx Z Z 2Ax = 2Bx 2Ax = 2Bx Z Z 2A6-10, 2B6-10 2Ay = 2By Z 2Ay = 2By Z 2Ay = 2By Z 2Ay = 2By Z 2Ay = 2By Z 2Ay = 2By Z 2Ay = 2By Z 2Ay = 2By Z
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Truth Tables
Configuration 4
(Continued) S0 = S1 = H 4-Bit Configuration Inputs/Outputs OE4 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H OE5 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H 1A1-4, 1B1-4 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx 1Ax = 1Bx Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 1A5-8, 1B5-8 1Ay = 1By 1Ay = 1By 1Ay = 1By 1Ay = 1By 1Ay = 1By 1Ay = 1By 1Ay = 1By 1Ay = 1By Z Z Z Z Z Z Z Z 1Ay = 1By 1Ay = 1By 1Ay = 1By 1Ay = 1By 1Ay = 1By 1Ay = 1By 1Ay = 1By 1Ay = 1By Z Z Z Z Z Z Z Z 2A3-6, 2B3-6 2Ax = 2Bx 2Ax = 2Bx 2Ax = 2Bx 2Ax = 2Bx Z Z Z Z 2Ax = 2Bx 2Ax = 2Bx 2Ax = 2Bx 2Ax = 2Bx Z Z Z Z 2Ax = 2Bx 2Ax = 2Bx 2Ax = 2Bx 2Ax = 2Bx Z Z Z Z 2Ax = 2Bx 2Ax = 2Bx 2Ax = 2Bx 2Ax = 2Bx Z Z Z Z 2A7-10, 2B7-10 2Ay = 2By 2Ay = 2By Z Z 2Ay = 2By 2Ay = 2By Z Z 2Ay = 2By 2Ay = 2By Z Z 2Ay = 2By 2Ay = 2By Z Z 2Ay = 2By 2Ay = 2By Z Z 2Ay = 2By 2Ay = 2By Z Z 2Ay = 2By 2Ay = 2By Z Z 2Ay = 2By 2Ay = 2By Z Z 1A9-10, 2B9-10 2A1-2, 2B1-2 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z 1Az = 1Bz 2Az = 2Bz Z
Inputs OE1 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H OE2 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H OE3 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H
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FSTUD16450
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC ) DC Switch Voltage (VS) (Note 3) DC Input Control Pin Voltage (VIN) (Note 4) DC Input Diode Current (lIK) VIN < 0V DC Output (IOUT ) Current DC VCC/GND Current (ICC/IGND) Storage Temperature Range (TSTG)
-0.5V to +7.0V -2.0V to +7.0V -0.5V to +7.0V -50 mA
128 mA
Recommended Operating Conditions (Note 5)
Power Supply Operating (VCC) Input Voltage (VIN) Output Voltage (VOUT) Free Air Operating Temperature (TA) 4.0V to 5.5V 0V to 5.5V 0V to 5.5V -40 C to +85 C
+/- 100 mA -65C to +150 C
Note 2: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: VS is the voltage observed/applied at either the A or B Ports across the switch. Note 4: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Note 5: Unused control inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC Symbol VIK VIH VIL VOH II IOZ RON Parameter Clamp Diode Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage Input Leakage Current OFF-STATE Leakage Current Switch On Resistance (Note 7) (V) 4.5 4.0-5.5 4.0-5.5 4.5-5.5 5.5 0 5.5 4.5 4.5 4.5 4.0 4.5 ICC Quiescent Supply Current 5.5 ICC 4 4 8 11 35 See Figure 4 1.0 10 1.0 7 7 12 20 50 3 10 1.5 Increase in ICC per Input 5.5 4.0 VIKU Voltage Undershoot 5.5 -2.0 mA V 2.5 2.0 0.8 TA = -40 C to +85 C Min Typ (Note 6) Max -1.2 Units V V V V A A A A A mA mA IIN = -18 mA IF S2 = HIGH 4.5V VCC 5.5V IF S2 = HIGH 4.5V VCC 5.5V S2 = VCC 0 VIN 5.5V VIN = 5.5V 0 A, B VCC VIN = 0V, IIN = 64 mA, S2 = 0V or VCC VIN = 0V, IIN = 30 mA, S2 = 0V or VCC VIN = 2.4V, IIN = 15 mA, S2 = 0V VIN = 2.4V, IIN = 15 mA, S2 = 0V VIN = 2.4V, IIN = 15 mA, S2 = VCC S2 = GND, VIN = VCC or GND, IOUT = 0 S2 = VCC, OE x = VCC, VIN = VCC or GND, IOUT = 0 S2 = VCC, OE x = GND, VIN = VCC or GND, IOUT = 0 One Input at 3.4V Other Inputs at VCC or GND, S2 = 0V One Input at 3.4V Other Inputs at VCC or GND, S2 = VCC 0.0 mA IIN -50 mA OEx = 5.5V
Note 6: Typical values are at VCC = 5.0V and T A = +25C Note 7: Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B) pins.
Conditions
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FSTUD16450
AC Electrical Characteristics
TA = -40 C to +85 C, Symbol Parameter CL = 50pF, RU = RD = 500 VCC = 4.5 - 5.5V Min tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ Propagation Delay Bus-to-Bus (Note 8) Output Enable Time Output Disable Time Sel (S0, 1) to Output Enable Time Sel (S0, 1) to Output Disable Time 1.5 1.5 1.5 1.5 Max 0.25 6.5 6.7 7.0 7.5 VCC = 4.0V Min Max 0.25 7.0 7.2 7.5 7.7 ns ns ns ns ns VI = OPEN VI = 7V for tPZL VI = OPEN for tPZH VI = 7V for tPLZ VI = OPEN for tPHZ VI = 7V for tPZL VI = OPEN for tPZH VI = 7V for tPLZ VI = OPEN for tPHZ Figures 2, 3 Figures 2, 3 Figures 2, 3 Figures 2, 3 Figures 2, 3 Units Conditions (S2 = 0V) Figure Number
Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
AC Electrical Characteristics: Translating Diode
TA = -40 C to +85 C, Symbol Parameter CL = 50pF, RU = RD = 500 VCC = 4.5 - 5.5V Min tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ Propagation Delay Bus-to-Bus (Note 9) Output Enable Time Output Disable Time Sel (S0, 1) to Output Enable Time Sel (S0, 1) to Output Disable Time 1.5 1.5 1.5 1.5 Max 0.25 10.0 9.0 11.0 10.0 ns ns ns ns ns VI = OPEN VI = 7V for tPZL VI = OPEN for tPZH VI = 7V for tPLZ VI = OPEN for tPHZ VI = 7V for tPZL VI = OPEN for tPZH VI = 7V for tPLZ VI = OPEN for tPHZ Figures 2, 3 Figures 2, 3 Figures 2, 3 Figures 2, 3 Figures 2, 3 Units Conditions (S2 = VCC) Figure Number
Note 9: This parameter is guaranteed by design but is not tested. This bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
Symbol CIN CI/O
(Note 10)
Parameter Typ 4 8 Max Units pF pF Conditions VCC = 5.0V, VIN = 0V VCC, OE = 5.0V, VIN = 0V
Control Pin Input Capacitance Input/Output Capacitance "OFF State"
Note 10: TA = +25C, f = 1 MHz, Capacitance is characterized but not tested.
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FSTUD16450
Undershoot Characteristic (Note 11)
Symbol VOUTU Parameter Output Voltage During Undershoot Min 2.5 TBD Typ VOH - 0.3 TBD Max Units V V S2 = V CC Conditions S2 = 0V, Figure 1
Note 11: This test is intended to characterize the device's protective capabilities by maintaining output signal integrity during an input transient voltage undershoot event.
FIGURE 1.
Device Test Conditions
Parameter VIN R1 = R2 VTRI VCC Value see Waveform 100K 11.0 5.5 Units V V V
Transient Input Voltage (VIN) Waveform
AC Loading and Waveforms
Note: Input driven by 50 source terminated in 50 Note: CL includes load and stray capacitance Note: Input Frequency = 1.0 MHz, tW = 500 ns
FIGURE 2. AC Test Circuit
FIGURE 3. AC Waveforms
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FIGURE 4.
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FSTUD16450
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary
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FSTUD16450 Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild's proven switch technology used for several years in its 74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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